1. Field of the Invention
The present invention relates to a semiconductor memory device, a memory device support and a memory module.
2. Related Art
FIG. 1 illustrates a prior art memory module. As shown, the memory module includes a support 100, which is usually a PCB (printed circuit board). A plurality of semiconductor memory chips 112 are mounted on each side of the support 100. The support 100 includes a plurality of vias and conductive lines (not shown) to connect the plurality of semiconductor memory chips 112 to terminals 114 of the memory module. The vias and conductive lines form control signal lines and internal data lines. The memory chips 112 on both sides of the support 100 are connected to the control signal lines such that the memory chips 112 receive the same control signals from the terminals 114. As a result, and as graphically shown, the memory chips 112 mounted on both sides of the support 100 may be conceptually thought of as outputting to a single data line 116. Stated another way, there is a single set of memory chips controlled by the same control signals, and such a memory module is said to have a rank of one. For example purposes, each memory chip 112 is also shown as outputting 4 bits at a time such that the memory module as a whole may transfer 72 bits over the data line 116.
In contrast to the single rank memory module of FIG. 1, FIG. 2 illustrates a prior art memory module having a rank of two. As shown in FIG. 2, a support 110 includes a first set of semiconductor memory chips 112′-1 mounted on the first side of the support 110 and a second set of semiconductor memory chips 112′-2 mounted on the opposing, second side of the support 110. The support 110 includes vias and conductive lines such that the first and second sets of semiconductor memory chips 112′-1 and 112′-2 are connected to terminals 114′. As is well known, the first and second sets of semiconductor memory chips 112′-1 and 112′-2 are connected to the control signal lines and internal data lines such that only one of the first and second sets of semiconductor memory chips 112′-1 and 112′2 are enabled at one time. Accordingly, while the first and second sets of semiconductor memory chips 112′-1 and 112′-2 are connected to the same terminals 114′, the memory module may be conceptually thought of as having two separate data lines 116′-1 and 116′-2.
For instance, usually one or more signals called chip select or enable signals are applied to at least one of the control lines to control which set of chips are enabled. If the chips select signal is set to a logic level zero, then the first set of semiconductor memory chips 112′-1 is enabled, and may be thought of as being connected to the first data line 116′-1. However, if the chip select signal is a logic 1, then the second set of semiconductor memory chips 112′-2 is enabled and may be thought of as connected to the second data line 116′-2. Because there are two separately selectable sets of semiconductor memory chips in this memory module, the rank of the memory module is said to be two. For example purposes, each memory chip 112′ is also shown as outputting 8 bits at a time such that the memory module as a whole may transfer 72 bits over the data line 116′1 or 116′-2.
FIG. 3 illustrates yet another prior art memory module. The memory module of FIG. 3 is similar of the memory module of FIG. 2 in that the rank of the memory module is two. However, the memory module of FIG. 3 includes stacks of semiconductor memory chips mounted on each side of a support. Namely, as shown in FIG. 3, the semiconductor module includes a support 20. A first side or face 21 of the support 20 includes a plurality of mounting locations 26-1 thru 26-n. A first set 22 of semiconductor memory devices 22-1 thru 22-n are respectively mounted at the mounting locations 26-1 thru 26-n. Similarly, a second side or face 23 of the support 20 includes a plurality of mounting locations 28-1 thru 28-n. A second set 24 of semiconductor memory device 24-1 thru 24-n are respectively mounted at the mounting locations 28-1 thru 28-n. Each of the first and second sets of semiconductor memory devices 22 and 24 has a structure such as shown in FIG. 4A.
FIG. 4A illustrates a prior art semiconductor memory device having a plurality of stacked dies or chips. In the example of FIG. 4A, the semiconductor memory device includes two semiconductor memory dies or chips 10-1 and 10-2. Each of the stacked dies or chips 10-1 or 10-2 has its inputs and outputs electrically connected to associated external pads in an array 12 of external pads on an external surface of the memory device. As is well known, the array of external pads 12 may be a ball grid array.
As shown in FIG. 4A, the array 12 includes a left side area 12-1, a center area 12-2 and a right side area 12-3. The center area 12-2 does not include external pads such that the array 12 is really a left side array 12-1 and a right side array 12-3. As further shown, each external pad in the left and right side arrays 12-1 and 12-3 are associated with particular signals, which are well known in the art. Because the signals associated with each pad are well known, they will not be discussed in detail. Instead, for the purposes of discussion, only the external pads highlighted in the left and right side arrays 12-1 and 12-3 will be discussed.
As shown, the left side array 12-1 includes external pads for a first clock enable signal CKE0 and a second clock enable signal CKE1. The first die 10-1 is connected to the external pad associated with first clock enable signal CKE0, and the second die 10-2 is connected to the external pad associated with the second clock enable signal CKE1. Accordingly, in this disclosure those external pads may also be referred to as the first and second clock enable external pads cke0 and cke1. Namely, for the array 12, upper case will denote the signal and lower case the pad. The right side array 12-3 includes respective external pads for first and second chip select signals CSB0 and CSB1, and further includes respective external pads for first and second on-die termination enable signals ODT0 and ODT1. The first die 10-1 is connected to the external pads associated with the first chip select signal CSB0 and first on-die termination enable signal ODT0. The second die 10-2 is connected to the external pads associated with the second chip select signal CSB1 and the second on-die termination enable signal ODT1.
The chip select signals CSB0 and CSB1 dictate whether the first chips 10-1 or the second chips 10-2 in the semiconductor memory devices 22 or 24 are enabled. The on-die termination signals ODT0 and ODT1 dictates whether the first chips 10-1 or the second chips 10-2 in the semiconductor memory devices 22 or 24 have on-die termination enabled, and the clock enable signals dictate whether the first chips 10-1 or the second chips 10-2 in the semiconductor memory devices 22 or 24 have their clocks enabled.
Returning to FIG. 3, the support 20 includes vias and conductive lines such that the first and second sets of semiconductor memory devices 22 and 24 are connected to terminals (not shown) such as shown in FIGS. 1 and 2. As is well known, the first and second sets of semiconductor memory devices 22 and 24 have the same external pads in the array 12 connected to the same control signal lines and terminals such that only the first chips 10-1 or the second chips 10-2 in the first and second sets of semiconductor memory devices 22 and 24 are enabled at one time. Accordingly, while the first and second sets of semiconductor memory devices 22 and 24 are connected to the same terminals, the memory module has a rank of two and may be conceptually thought of as having two separate data lines.
FIG. 3 illustrates two example control signal lines CON1L and CON2L as well as the clock signal line CKL. The first and second control signal lines CON1L and CON2L each carry a respective control signals CON1 and CON2, while the clock signal line CKL carries the clock signal CK. However, it will be appreciated that more than just the two illustrated control signal lines CON1L and CON2L exist. For example the first and second control signals CON1 and CON2 may be the first and second clock enable signals CKE0 and CKE1, the first and second chip select signals CSB0 and CSB1, or the first and second on-die termination signals ODT0 and ODT1. Each control signal line CON1L, CON2L and CKL are terminated by a resistance Rtt connected to a termination voltage Vtt.
FIG. 4B illustrates the connection a corresponding pair of memory devices to the support in FIG. 3. In particular, FIG. 4B illustrates a portion of the connections of a memory device 22 and oppositely facing, or corresponding, memory device 24 to the support 20. As shown, a pin or pad 1c1 of the first die 10-1 in the memory device 22 is electrically connected to an external pad c1 in the array 12, and a pin or pad 2c2 of the second die 10-2 in the memory device 22 is electrically connected to an external pad c2 in the array 12. In this example, the external pads c1 and c2 may correspond to the first and second clock enable external pads cke0 and cke1, respectively. Furthermore, the clock signal pad 1ck of the first die 10-1 of the memory device 22 and the clock signal pad 2ck of the second die 10-2 are connected to the external clock signal pad ck in the array 12.
Similarly, for the opposite facing semiconductor memory device 24, a pin or pad 1c1′ of the first die 10-1 in the memory device 24 is electrically connected to an external pad c1′ in the array 12, and a pin or pad 2c2′ of the second die 10-2 in the memory device 24 is electrically connected to an external pad c2′ in the array 12. In this example, the external pads c1′ and c2′ may correspond to the first and second clock enable external pads cke0 and cke1, respectively. Furthermore, the clock signal pad 1ck′ of the first die 10-1 of the memory device 24 and the clock signal pad 2ck′ of the second die 10-2 are connected to the external clock signal pad ck′ in the array 12.
As shown in FIG. 4B, the semiconductor memory device 24 is flipped with respect to the semiconductor memory device 22 and the left side array 12-1 of the semiconductor memory device 24 faces opposite the right side array 12-3 of the semiconductor memory device 22. Likewise, the right signal array 12-3 of the semiconductor memory device 24 faces opposite the lefts side array 12-1 of the semiconductor memory device 22.
The external pad c1 of the memory device 22 is connected to a first control signal pad C1 of the support 20, and the first control signal pad C1 is connected by a first control signal via C1-1 to the first control signal line CON1L at a point b. The corresponding external pad c1′ of the memory device 24 is connected to a first control signal pad C1′ of the support 20, and the first control signal pad C1′ is connected by a first control signal via C1-1′ to the first control signal line CON1L at a point b′.
The external pad c2 of the memory device 22 is connected to a second control signal pad C2 of the support 20, and the second control signal pad C2 is connected by a second control signal via C2-1 to the second control signal line CON2L at a point a. The corresponding external pad c2′ of the memory device 24 is connected to a second control signal pad C2′ of the support 20, and the second control signal pad C2′ is connected by a second control signal via C2-1′ to the second control signal line CON2L at a point a′.
The external clock signal pad ck of the memory device 22 is connected to a clock signal pad CKP of the support 20, and the corresponding external clock signal pad ck′ of the memory device 24 is connected to a clock signal pad CKP′ of the support 20. The clock signal pads CKP and CKP′ are connected by a through-hole via CK1-1 to the clock signal line CKL at point d.
As will be appreciated, the first dies 10-1 in the first and second memory devices 22 and 24 form a first set of chips controlled by the first set of control signals (e.g., clock enable signal CKE0, chip select signal CSB0, etc.), and the second dies 10-2 in the first and second memory devices 22 and 24 form a second set of chips controlled by the second set of control signals (e.g., clock enable signal CKE1, chip select signal CSB1, etc.). Accordingly, the rank of the memory module illustrated in FIG. 3 is two.
As will be further appreciated, because of the separation between points b and b′ as well as a and a′, the control signals on the first and second control signal lines CON1L and CON2L are received at different times by the first and second semiconductor memory devices 22 and 24. This is referred to as skew, and may cause timing problems in the operation of the memory module.
Also, a number of vias in the support 20 are used to connect the pads of the support 20 to the signal lines CON1L, CON2L and CKL. As is known, the support 20 is generally a PCB, which is comprised of several layers. The signal lines CON1L, CON2L and CKL are formed on an internal layer of the PCB. Accordingly vias are used to electrically connect pads on external layers of the PCB to the signal lines. FIG. 5 illustrates different types of vias: a blind via, a buried via and a through hole via. Generally, a via is a hole through one or more layers of the PCB that has been filled with conductive material. A blind via leads from one of the external layers to one of the internal layers of the PCB. A buried via leads from one internal layer to another internal layer of the PCB. A through hole via leads from one external layer to the other external layer of the PCB. As shown in FIG. 4B, a through hole via is used to connect clock signal pads CKP and CKP′ to the clock signal line CKL. Also, four blind vias C1-1, C1-1′, C2-1 and C2-1′ are used to connect the pads C1, C1′, C2 and C2′ to their respective control signal lines CON1L and CON2L.